1. Technical Field
The present disclosure relates to a sigma-delta (Σ-Δ) modulator and a fractional-N frequency synthesizer comprising same, and more particularly, to a multi-bit multiple-order interpolative Σ-Δ modulator and a fractional-N phase-locked loop (PLL) frequency synthesizer comprising the same.
2. Discussion of the Related Art
PLL frequency synthesizers synthesize desired signals using a reference signal and control a ratio of the synthesized signal to the reference signal using a controller.
PLL frequency synthesizers may employ an integer-N technique and a fractional-N technique. The integer-N technique uses a fixed integer N to divide an output frequency, and the fractional-N technique uses a number N to divide the output frequency which is selected among two or more integers (e.g., N is varied between two or more integers such that the average value of N is fractional). As a result, a divisor is fractional when using the fractional-N technique due to interpolation of each number N selected for every dividing operation.
It may be difficult to meet certain specifications when employing the integer-N technique due to a trade-off between loop bandwidth and channel spacing, while the fractional-N technique alleviates design restrictions on PLLs permitting a broader loop bandwidth while maintaining narrow channel intervals.
The Σ-Δ modulator provides a control signal necessary for selecting N in the fractional-N technique.
The Σ-Δ modulator may be classified as a multistage-noise-shaping (MASH) Σ-Δ modulator and an interpolative Σ-Δ modulator. As shown in FIG. 1, a first-order MASH Σ-Δ modulator forms an independent loop and is cascaded to another loop in order to construct a high-order modulator. Thus, the high-order modulator can be unconditionally stable and use most of an input range. However, the overall structure of the high-order modulator is complicated. The cascaded first-order modulator causes poor idle-tone characteristics. In order to improve the idle-tone characteristics, each node must vary an output signal of the MASH Σ-Δ modulator by using an independent dither that does not affect another node.
When the MASH Σ-Δ modulator is a multi-bit modulator, a pass-band gain level of the multi-bit modulator is high, resulting in output value changes over a large range. Accordingly, in a fractional-N frequency synthesizer using the MASH Σ-Δ modulator, a non-linear error in a phase/frequency detector increases with an increase of the range of output value changes, thereby greatly limiting the performance of the fractional-N frequency synthesizer.
The interpolative Σ-Δ modulator has a structure as shown in FIG. 2. The structure of the interpolative Σ-Δ modulator is simpler than that of the MASH Σ-Δ modulator. In addition, when the interpolative Σ-Δ modulator is used as a multi-bit modulator, the interpolative Σ-Δ modulator has a lower pass-band gain level than the MASH Σ-Δ modulator, resulting in output value changes over a smaller range than with a MASH Σ-Δ modulator.
In consideration of the above, a fractional-N frequency synthesizer using a single-bit 4th-order Σ-Δ modulator has been proposed. The single-bit 4th-order Σ-Δ modulator is not as stable as the MASH Σ-Δ modulator and thus guarantees stability over only a limited input range. In other words, a dead band occurs over the full input range. As a result, as shown in FIG. 3, the single-bit 4th-order Σ-Δ modulator uses only 50% of the full input range and maps an output value into N−1 or N+1. This results in 1 bit loss and an increase in quantization noise by 6 dB.
In addition, a quantization noise transfer function of the single-bit 4th-order Σ-Δ modulator functions like a high-pass filter. When the single-bit 4th-order Σ-Δ modulator is of an interpolative type, a pass band gain level must be less than a threshold in order to maintain stability. The pass band gain level is generally adjusted using a Butterworth filter coefficient. Since a total amount of the quantization noise is maintained at a constant level, the threshold in order to maintain stability and a corner frequency of the pass band gain level show a trade-off tendency as seen in FIG. 4. In other words, the pass band gain level increases when the corner frequency increases, and the pass band gain level decreases when the corner frequency decreases.
When fs is an operation frequency, the maximum corner frequency that guarantees the stability of the single-bit 4th-order Σ-Δ modulator is 0.06(fs). FIGS. 5A and 5B respectively show a quantization noise transfer curve of the single-bit 4th-order Σ-Δ modulator and the output of a PLL with respect to frequency. In FIG. 5B, slanted line 60 denotes out-of-band phase noise of a voltage controlled oscillator (VCO) of the PLL. As can be seen in FIG. 5B, phase noise of the PLL becomes increasingly worse when the frequency approaches the corner frequency of the single-bit 4th-order Σ-Δ modulator.
Lastly, the single-bit 4th-order Σ-Δ modulator without dithering causes unwanted idle-tones. FIG. 6 shows the result of autocorrelation for 2000 outputs of the single-bit 4th-order Σ-Δ modulator. As can be seen in FIG. 6, the autocorrelation results vary within a large range.
Accordingly, there is a need for a Σ-Δ modulator and a stable fractional-N frequency synthesizer using the Σ-Δ modulator. SUMMARY OF THE INVENTION
A fractional-N frequency synthesizer, according to an embodiment of the present invention, includes a phase detector, a voltage controlled oscillator, a divider, and a sigma-delta modulator. The phase detector detects a phase difference between a reference signal and a feedback signal. The voltage controlled oscillator receives a phase difference control signal based on the detected phase difference and oscillates a signal with a frequency based on the detected phase difference. The divider selects a value from at least three integers according to a predetermined selection signal, divides the frequency of the oscillated signal output from the voltage controlled oscillator by the selected value, and outputs a divided signal as a feedback signal to the phase detector. The sigma-delta modulator adds a predetermined input value to an internal feedback value, successively accumulates added values, quantizes the an accumulated value to at least three levels, and converts a quantized value into the predetermined selection signal.
The sigma-delta modulator may include a plurality of operation units for adding the predetermined input value to the internal feedback value and for successively accumulating the added values, a quantizer for quantizing the accumulated value output from a last one of the plurality of operation units to a plurality of bits and for outputting the quantized value as the predetermined selection signal to the divider, and a plurality of multipliers for outputting feedback coefficients as internal feedback values to each of the plurality of operation units, wherein the feedback coefficients are determined according to a quantized level corresponding to the plurality of bits. The feedback coefficients may be symmetrical values spaced at equal intervals around a middle level of the at least three levels. The feedback coefficients may be converted into bit streams with binary values. The fractional-N frequency synthesizer may further include a control signal generator for receiving a plurality of bit values output from the quantizer and for outputting a minimum number of control signals depending on symmetrical values of the bit streams. The control signal generator may include a gray coder for converting the plurality of bit values into a gray code, a plurality of control signal generating units for receiving the gray code and for outputting the control signals, a plurality of inverters for inverting outputs of the plurality of control signal generating units. The multipliers may include connections for outputting the bit streams from the control signals of the control signal generator directly to the plurality of operation units.
A sigma-delta modulator, according to an embodiment of the present invention, includes a plurality of operation units, a quantizer, and a plurality of multipliers. The plurality of operation units add input values to internal feedback values and successively accumulate the added values up to a fourth order. The quantizer quantizes an accumulated value output from a last one of the plurality of operation units into a plurality of bits. The plurality of multipliers output feedback coefficients as internal feedback values to each of the plurality of operation units, wherein the feedback coefficients are determined according to a quantized level corresponding to the plurality of bits.
The feedback coefficients may be symmetrical values spaced at equal intervals around a middle level of a plurality of levels output from the quantizer. The feedback coefficients may be converted into bit streams with binary values. The sigma-delta modulator may further include a control signal generator for receiving a plurality of bit values output from the quantizer and for outputting a minimum number of control signals depending on symmetrical values of the bit streams. The control signal generator may include a gray coder for converting the plurality of bit values into a gray code, a plurality of control signal generating units for receiving the gray code and for outputting the control signals, and a plurality of inverters for inverting outputs of the control signal generating units. The multipliers may include connections for outputting the bit streams from the control signals of the control signal generator directly to the plurality of operation units.
A frequency synthesizer, in accordance with an embodiment of the present invention, includes a phase detector for detecting a phase difference between a reference signal and a feedback signal, a voltage controlled oscillator for receiving a phase difference control signal based on the detected phase difference, and for outputting a signal with a frequency based on the detected phase difference, a divider for selecting a value from a plurality of integers according to a predetermined selection signal, for dividing the frequency of the signal output from the voltage controlled oscillator by the selected value, and for outputting a divided signal as a feedback signal to the phase detector, and a modulator for adding a predetermined input value to an internal feedback value, for successively accumulating added values, for quantizing an accumulated value to a plurality of levels, and for converting a quantized value into the predetermined selection signal.
The modulator may include a plurality of operation units for adding the predetermined input value to the internal feedback value and for successively accumulating the added values, a quantizer for quantizing the accumulated value output from a last one of the plurality of operation units to a plurality of bits and for outputting the quantized value as the predetermined selection signal to the divider, and a plurality of multipliers for outputting feedback coefficients as internal feedback values to each of the plurality of operation units, wherein the feedback coefficients are determined according to a quantized level corresponding to the plurality of bits.
The feedback coefficients may be symmetrical values spaced at equal intervals around a middle level of the plurality of levels.